EW31244SL7QV Datasheet, PDF (22/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Overview
2.1
2.2
Features
• Four SATA Ports at 1.5 Gbits/s
• Compliant with Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e
• 64-bit/133MHz PCI-X Bus. Backwards compatible to PCI 32-bit/33 MHz and 64-bit/66 MHz
• Supports native PCI IDE
• Hot-Plug Drives
• Supports Master/Slave Mode for Compatibility with existing Operating Systems
• Supports SATA Direct Port Access
• Independent DMA Masters for each SATA Port
• 3.3V and 2.5V Supply, 2W maximum
PCI-X Interface
The 64-bit, 133 MHz PCI-X interface is fully compliant with the PCI Local Bus Specification,
Revision 2.2 and the PCI-X Addendum to the Local Bus Specification, Revision 1.0. The PCI-X
bus supports up to 1064 Mbytes/s transfer rate of burst data. The GD31244 is backwards
compatible with 32-bit/33 MHz, 32-bit/66 MHz and 64-bit/66 MHz operation. The GD31244
contains internal registers and support circuitry to implement complete Plug-n-Play functionality,
which allows hardware and firmware to resolve all setup conflicts for the user. The GD31244
supports both slave and master data transfers.
During system initialization, the host system Configuration Manager reads the configuration space
of each PCI-X device. After hardware reset, the GD31244 only responds to PCI-X Configuration
cycles in anticipation of being initialized by the Configuration Manager. Each PCI-X device is
addressable individually by the use of unique IDSEL signals which, when asserted, indicate that a
configuration read or write is occurring to this device. The Configuration Manager reads the setup
registers of each device on the PCI-X bus and then, based on this information, assigns system
resources to each supported function through Type 0 configuration reads and writes. Type 1
configuration cycles are ignored. This scheme allows the GD31244 to be relocated in the memory
and I/O space. Interrupts, DMA Channels and other system resources may be reallocated
appropriately.
22
April 2004
Developer’s Manual