EW31244SL7QV Datasheet, PDF (215/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.11 SU PCI DPA Mode DMA Registers
This section defines the DPA DMA Registers.
5.10.11.1 SU PCI DPA Upper DMA Descriptor Table
Pointer Register - SUPDUDDTPR
Table 130.
The SU PCI DPA Upper DMA Descriptor Table Pointer Register contains the upper 32-bit PCI
address of the 64-bit PCI address. In PCI IDE mode, the SU PCI DPA Upper DMA Descriptor
Table Pointer Register is not used. This register allows the descriptor table to be located in any
4 Gbyte memory space.
SU PCI DPA Upper DMA Descriptor Table Pointer Register - SUPDUDDTPR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
31:00
DPA Mode BAR0 Offset
Port 0 = 264H, Port 1 = 464H
Port 2 = 664H, Port 3 = 864H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Default
Description
0000 0000H PCI Address - is the PCI source/destination upper address.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Developer’s Manual
April 2004
215