EW31244SL7QV Datasheet, PDF (35/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.1 PROGRAM Command
In order to program the EEPROM, two separate commands must be executed. Prior to each
PROGRAM command, the device must be write enabled through the WREN command. The
PROGRAM command may then be executed. Also, the address of the memory location(s) to be
programmed must be outside the protected address field location selected by the Block Write
Protection Level. During an internal self-timed programming cycle, all commands will be ignored
except the RDSR command.
The READY bit (bit 0) in the status register of the EEPROM may be determined by initiating a
RDSR command. When HIGH, the program cycle is still in progress. When LOW, the program
cycle has ended. Only the RDSR command is enabled during the program cycle. Single
PROGRAM command programs 1, 2 or 4 consecutive bytes within a page if it is not write
protected. The starting byte should be word aligned if 16-bit and dword aligned if 32-bit. The data
of all other bytes on the same page will remain unchanged. The same byte cannot be reprogrammed
without erasing the whole sector first. The EEPROM will automatically return to the write disable
state at the completion of the PROGRAM cycle. The write memory (PROGRAM) operation for
four bytes is shown in Figure 6.
Note: When the device is not write enabled with a WREN command, the device will ignore the
PROGRAM command and will return to the standby state, when SCS# is brought high. A new
SCS# falling edge is required to re-initiate the serial communication.
Figure 6. Write Memory (PROGRAM) Operation, 4 Byte
SCS#
0 4 8 12 16 20 24 28 32 36 40 44 48 52 54 56
SCLK
SDO
00000011
23-bit Address
Byte 0 Byte 1 Byte 2 Byte 3
76543210 76543210 76543210 76543210
To issue a PROGRAM command:
1. Issue a WREN command as described elsewhere.
2. Issue a RDSR command to read that the RDY# bit is LOW and the WEN bit is HIGH in the
EEPROM’s Status Register to ensure that the EEPROM is ready to receive a write command.
3. When RDY# is not low, continue issuing RDSR commands until RDY# becomes low.
4. Issue a PROGRAM command by and 8-bit, 16-bit or 32-bit write to the ROM address.
Developer’s Manual
April 2004
35