EW31244SL7QV Datasheet, PDF (114/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.6
Table 44.
SU Class Code Register - SUCCR
Class Code Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2. Auto
configuration software reads this register to determine the PCI device function.
SU Class Code Register - SUCCR
PCI
Attributes
23
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI Configuration Address Offset
09H - 0BH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
23:16
15:08
07:04
03:00
Default
Description
01H
Base Class - Mass Storage Device
Sub Class -
Varies with
• When in Direct Port Access Mode (DPA_MODE# = low)
external state of = 06H - DPA Mode
DPA_MODE# pin _{• When in PCI IDE Mode (DPA_MODE# = high)}
= 01H - PCI IDE
Programming Interface -
Varies with
• When in Direct Port Access Mode (DPA_MODE# = low)
external state of = 0000₂
DPA_MODE# pin _{• When in PCI IDE Mode (DPA_MODE# = high)}
= 1000₂ - Bit 7 set identifies the PCI IDE device as a Bus Master
Programming Interface -
Varies with
• When in Direct Port Access Mode (DPA_MODE# = low)
external state of = 0000₂
DPA_MODE# pin _{• When in PCI IDE Mode (DPA_MODE# = high)}
= 0101₂ - SATA Unit supports Native-PCI mode only
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
114
April 2004
Developer’s Manual