EW31244SL7QV Datasheet, PDF (227/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.5 SU PCI DPA PHY Feature Register - SUPDPFR
Table 139.
The SU PCI DPA PHY Feature Register is a 32-bit register. This register may be used to enable the
full voltage swing on all the SATA ports, for extended applications such as backplanes or external
cables.
SU PCI DPA PHY Feature Register - SUPDPFR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv ro rv rw rv rv rv rv rv rv rv rv rv rv rv rv rv rv
PCI IDE Mode BAR5 Offset
= 040H,
DPA Mode BAR0 Offset
Port 0 = 340H, Port 1 = 540H
Port 2 = 740H, Port 3 = 940H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:20
19:17
16
15
14
13
12
11:10
09
08
07:00
Default
000H
000₂
0₂
0₂
0₂
0₂
0₂
00₂
0₂
0₂
00H
Description
Reserved.
Reserved.
Reserved.
Reserved.
Full Voltage Swing - When HIGH, the transmitter output buffer for all of the ports will be in high swing
mode for extended applications such as backplanes or external cables. When LOW, the transmitter
output is compliant to Serial ATA specifications.
When HIGH, the serialized data in the transmitter is wrapped around to the input of the Clock Recovery
Unit (CRU) in the receiver. When LOW, the RXxP/RXxN input is used by the receiver.
When HIGH, the cable equalizer within the receiver’s input buffer is disabled. When LOW, the cable
equalizer is enabled.
These two bits select the receiver’s signal detect threshold level as follows:
• 00 Nominal Setting: ~75 - 150 mV
• 01 This reduces the nominal threshold by approximately ~25 mV
• 10 This increases the nominal threshold by approximately ~25 mV
• 11 This increases the nominal threshold by approximately ~50 mV.
Bit 8 must be set HIGH for Bit 9 to enable or disable the SERDES Tx buffers. With Bit 8 set HIGH and
Bit 9 LOW, the Tx pins are enabled and driven from the core logic value. With Bit 8 set HIGH and Bit 9
set HIGH, the SERDES Tx buffer is disabled.
Bit 8 is the mux control that selects between Bit 9 or OOB logic to enable or disable the SERDES Tx
pins. When HIGH, control is from Bit 9. When LOW, SERDES Tx buffer is enabled when the OOB
sequence is active (while JTAG scan is not active).
Reserved.
Developer’s Manual
April 2004
227