EW31244SL7QV Datasheet, PDF (72/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.2.5 SATA Superset Registers
The SATA Superset Registers, define two sets of registers. These registers are specific to the Serial
ATA Specification, hence superset.
The Serial ATA Specification defines an additional block of registers mapped separately and
independently from the ATA Command Block Registers for additional status and error information
and allow control of capabilities unique to Serial ATA. These registers referred to as the Serial ATA
Status and Control Registers (SCRs) are organized as 16 contiguous 32-bit registers. The current
specification defines three registers only, and the remaining thirteen are reserved for future
implementation. The defined SCRs are as follows:
• SStatus Register
• SError Register
• SControl Register
The Serial ATA protocol also provides additional SATA specific commands. The Serial ATA
defines two Frame Information Structures (FIS) that are not used by the current ATA Command set.
However, these FISs may be used to enable new device capabilities.
• BIST Activate (Bidirectional)
• DMA Setup - Device to Host or Host to Device (Bidirectional)
Table 27 shows the SATA Interface Registers mapping when in the Direct Port Access mode for
SATA Port 0. Refer to Section , “The SATA Unit may be set up during system reset to execute in
one of the following modes. Each mode provides a different programming interface. The
DPA_MODE# external strap signal is sampled during the rising edge of PCI reset, to determine the
operation mode.” on page 62 for further details on the mapping of the registers based on the
specific programming interface. When in PCI IDE mode, the super registers of a device on a given
channel are selected using the DEV bit of the Device/Head register (bit 4). A channel (primary or
secondary) is selected using bit 16 of the APT Control Register. Refer to Section 5.10.3.8, “SU IDE
Device/Head Register - SUIDR” on page 173 and Section 5.10.2.30, “SU Extended Control and
Status Register 0 - SUECSR0” on page 138. Also, when in PCI IDE mode, the superset registers
are accessed using Base Address Register 5. Refer to Section 5.10.2.16, “SU Base Address
Register 5 - SUBAR5” on page 124.
Note: The superset registers when in PCI IDE mode are accessed using SUBAR5 starting at offset 000H.
For example, Table 27 shows the first register starting at offset 300H, 304H, 308H and so on in
DPA mode. In PCI IDE mode, the registers start at offset 00H, 004H, 008H and so on.
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April 2004
Developer’s Manual