EW31244SL7QV Datasheet, PDF (98/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.7
Serial ATA Bus and Device Error Conditions
This section describes error handling that are specific to the Serial ATA bus and Serial ATA device.
5.7.1
Serial ATA Device Error Conditions
These are error conditions that are generated by the SATA device itself. For example, when an ATA
command is not supported by a device, the device will respond by returning a command-aborted
error condition. The SATA device reports error conditions through the Command Block Status and
Error registers. The bits in the Error register are only valid when the ERR bit (bit 0) of the Status
register is set. A device reports error conditions by sending a Device-to-Host Register FIS or a PIO
Setup FIS.
5.7.2 Serial ATA Bus and Protocol Error Conditions
Table 34.
Serial ATA bus and protocol related errors are reported in the SATA SError register. Some of the
errors reported may generate interrupts that are posted in the SATA Interrupt Pending register.
Refer to Section 5.10.8.1, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194 and
Section 5.10.12.2, “SU PCI DPA SATA SError Register - SUPDSSER” on page 222. Table 34
summarizes all the SATA bus related error conditions reported by the GD31244 controller.
31244 Controller Serial ATA Protocol and Bus Error Conditions (Sheet 1 of 2)
Bit
31-26
25
24
23
22
21
20
19
18
Description
Reserved
DIAG_F - Invalid FIS Type:
When set to one, this bit indicates that the FIS type field was not recognized. For example the FIS is
invalid. This bit is cleared by writing a 1 to it.
DIAG_T - Reserved, not implemented.
DIAG_S - Reserved, not implemented.
DIAG_H - Handshake Error:
When set to one, this bit indicates that one or more R_ERR handshake response was received in
response to frame transmission. Such errors may be the result of a CRC error detected by the receiver.
This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit 3, 11, 19, and 27 of the
SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to Table 116, “SU PCI
DPA Interrupt Pending Register - SUPDIPR” on page 194.
DIAG_C - CRC Error:
When set to one, this bit indicates that one or more CRC errors occurred. This bit is set when a CRC
error is detected when receiving a Data FIS only. This bit is cleared by writing a 1 to it. This bit is
reported as an interrupt on bit 6, 14, 22, and 30 of the SATA Interrupt Pending register for SATA ports 0,
1, 2, and 3 respectively. Refer to Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on
page 194.
DIAG_D - Disparity Error:
When set to one, this bit indicates that incorrect disparity was detected one or more times since the last
time this bit was cleared. This bit is set when a Disparity error is detected when receiving a Data FIS
only. This bit is cleared by writing a 1 to it.
DIAG_B - not implemented.
DIAG_W - Comm Wake:
When set to one, this bit indicates that a Comm Wake was detected by the PHY. This bit is cleared by
writing a 1 to it. The default value after reset is 0₂. After Comm Wake is detected, the value will change
to 1₂.
98
April 2004
Developer’s Manual