EW31244SL7QV Datasheet, PDF (210/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.9.8
Table 125.
SU PCI DPA Device/Head Register - SUPDDR
This SU PCI DPA Device/Head Register is an 8-bit read/write register. The content of the SU PCI
DPA Device/Head Register is a command parameter. The content of this register must be loaded
before the SU PCI DPA Command Register is written. The content of the SU PCI DPA
Device/Head Register is command dependent. Refer to the AT Attachment with Packet Interface-6
(ATA/ATAPI-6) Specification.
SU PCI DPA Device/Head Register - SUPDDHR
PCI
Attributes
7
4
0
rv rw rv rv rw rw rw rw
DPA Mode BAR0 Offset
Port 0 = 218H, Port 1 = 418H
Port 2 = 618H, Port 3 = 818H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07
Reserved
Logical Addressing Mode - This bit indicates the addressing mode:
06
0 = CHS Mode
1 = LBA Mode
05
04
03:00
Reserved
Device
Dependent ^{a Reserved.}
Head - This field is dependent on the device access methods. There are three methods:
• CHS addressing: this field indicates the head number for the Cylinder/Head/Sector format.
• 28-bit LBA addressing: This field is used for bit positions LBA[27:24] of the 28-bit addressing
LBA[27:0].
• 48-bit LBA Mode: These bit are not part of the 48-bit LBA address, but need to be set to 1111₂.
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a signature value. The signature
value is device dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
210
April 2004
Developer’s Manual