EW31244SL7QV Datasheet, PDF (43/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.9
3.1.9.1
Serial EEPROM SPI Interface – Address 90h
Programming Details
This module implements a controller for interfacing to a serial EEPROM using the SPI (Serial
Peripheral Interface) standard. The controller sits between a PCI core's application interface and
the serial device. It contains a state machine that accesses the ROM 1, 2 or 4 times for each PCI
transaction based on the byte enables.
Reads and writes are done through the PCI expansion port defined by CR30 in configuration space.
Reads from the serial device are very slow. The controller outputs a FIFO write signal to the PCI
core upon completion of the read operation. Since the FIFO is empty until this time, the host read
transaction will time-out and be retried by the PCI chipset until the controller writes the data into
the FIFO. The design will fail if the host aborts retries or reorders transactions to the PCI target. A
burst read transaction will be slowed down into a repetition of {retry, retry, ..., retry, read 1 data
phase then disconnect without data}.
Writes to the serial device must be performed by a special device driver that polls the device status
register to determine when the write is done. The next write may then be executed. Each write is
composed of two operations. The host must issue a write enable command followed by a write data
command of 1, 2 or 4 bytes. Burst writes are not allowed. Furthermore, the set of all write pairs
must be proceeded by one of the two erase commands. When the host attempts to write a
subsequent data value before the first completes, the PCI core will complete the transaction and
queue up the FIFO. The queue comes into play when the PCI bus write transaction period is less
than the static target state machine cycle time and FIFO starts to fill up. To avoid overflowing the
queue and causing the host to do retries, the serial EPROM write driver should not issue a
subsequent write until the current one is complete.
The host issues all commands except the read command through a register set in configuration
space. The register set is composed of command, control and data registers. The host writes the
command type to the command register after setting up the control and data registers as necessary.
The controller starts when the command register is written. The host then polls the status register to
determine when the command is complete. For read commands, except READ, the data register
will contain the result when done.
Developer’s Manual
April 2004
43