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| EW31244SL7QV Datasheet, PDF (214/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller | |||
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Intel® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.10.2 SU PCI DPA Device Control Register - SUPDDCTLR
Table 129.
The SU PCI DPA Device Control Register is an 8-bit write-only register. The SU PCI DPA Device
Control Register is used to initiate a software reset to the device. Refer to the AT Attachment with
Packet Interface-6 (ATA/ATAPI-6) Specification.
SU PCI DPA Device Control Register - SUPDDCTLR
PCI
Attributes
7
43
0
rv rv rv rv rv wo rv rv
DPA Mode BAR0 Offset
Port 0 = 229H, Port 1 = 429H
Port 2 = 629H, Port 3 = 829H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
WO = Write Only
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07
02
Reserved.
06
02
Reserved.
05
02
Reserved.
04
02
Reserved.
03
02
Reserved.
02
02
SRST - This bit is used by software to perform a device reset. Writing a 1 requests the device to start the
reset sequence, and writing a 0 request the device to terminate reset.
01
02
Reserved.
00
02
Reserved. This bit shall always be cleared.
214
April 2004
Developerâs Manual
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