EW31244SL7QV Datasheet, PDF (135/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.27 SPI Control Register - SPICNTR
Serial Peripheral Interface (SPI) Control Register definition of this 8 bit register is described in
Table 65. The host writes the control register to specify the sectors of the serial EEPROM to erase.
Note that the set of all write pairs must be proceeded by one of the two erase commands with the
sectors specified in the control register.
Table 65. SPI Control Register - SPICNTR
PCI
Attributes
15
12
8
rv rv rv rv rv rv rw rw
Bit
15:10
9:8
Default
00h
00b
PCI Configuration Address Offset
91
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Reserved.
Sector address [1:0]. Selects 1 of 4 sectors for the sector erase command 52h. It must be set prior
or simultaneously with writing the SECT_ERASE command to the SPI Command Register.
Developer’s Manual
April 2004
135