EW31244SL7QV Datasheet, PDF (111/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.3
Table 41.
SU Command Register - SUCMD
SU Command Register bits adhere to the definitions in the PCI Local Bus Specification,
Revision 2.2 and in most cases, affect the behavior of the PCI SU and devices on the PCI bus.
SU Command Register - SUCMD
PCI
Attributes
15
12
8
4
0
rv rv rv rv rv rv rw rw ro rw ro rw ro rw rw rw
PCI Configuration Address Offset
04H - 05H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessib
Bit
15:10
09
08
07
06
05
04
03
02
01
00
Default
Description
000000₂ Reserved
0₂
Fast Back to Back Enable - When cleared, the SATA Unit interface is not allowed to generate fast
back-to-back cycles on its bus. Ignored when operating in the PCI-X mode.
0₂
SERR# Enable - When cleared, the SATA Unit interface is not allowed to assert SERR# on the PCI
interface.
0₂
Address/Data Stepping Control - The SATA Unit does not support address stepping.
0₂
Parity Error Response - When set, the SATA Unit takes normal action when a parity error is
detected. When cleared, parity checking is disabled.
0₂
VGA Palette Snoop Enable - The SATA Unit interface does not perform VGA palette snooping.
Memory Write and Invalidate Enable - When set, SATA Unit may generate MWI commands. When
0₂
clear, SATA Unit use Memory Write commands instead of MWI. Ignored when operating in the PCI-X
mode.
0₂
Special Cycle Enable - The SATA Unit interface does not respond to special cycle commands in any
way. Not implemented and a reserved bit field.
Bus Master Enable - The SATA Unit interface may act as a master on the PCI bus. When cleared,
0₂
disables the device from generating PCI accesses. When set, allows the device to behave as a PCI
bus master.
Memory Enable - Controls the SATA Unit response to PCI memory addresses. When cleared, the
0₂
SATA Unit does not respond to any memory access on the PCI bus. The SATA port registers are
memory-mapped in DPA mode.
I/O Space Enable - Controls the SATA Unit response to I/O transaction. When cleared, the SATA
0₂
Unit does not respond to I/O access on the PCI Bus. The SATA Port registers are I/O-mapped in PCI
IDE mode.
Developer’s Manual
April 2004
111