EW31244SL7QV Datasheet, PDF (146/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.38 SU Transaction Control 2 Register SUTC2R
Table 76.
This register provides secondary transaction control.
SU Transaction Control 2 Register- SUTC2R
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw ro ro ro ro ro ro ro ro ro ro rw rw rw rw rw rw rw rw rw rw rw _rw rw rw
PCI Configuration Address Offset
CC-CF
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
Master request (memory read) byte count/byte enable select.
• 0 = Byte enables valid. In PCI mode, a burst transaction cannot be performed using memory read
31
1
command 6h.
• 1 = DWORD byte count valid (default). In PCI mode, the memory read byte enables are
automatically generated by the core.
Master request (I/O and CR cycles) byte count/byte enable select.
30
0
• 0 = Byte enables valid
• 1 = DWORD byte count valid.
Master (retry) deferred write enable (allows read requests to pass).
PCI mode I/O and memory transactions only.
29
0
• 0 = New read requests are not accepted until the current write cycle completes. Reads cannot
pass writes.
• 1 = New read requests are accepted, even when there is a write cycle pending. Reads can pass
writes.
Master (retry) deferred read enable (allows read/write requests to pass.) PCI mode I/O and
memory transactions only.
28
0
• 0 = New read/write requests are not accepted until the current read cycle completes. Read/Write
requests cannot pass reads.
• 1 = New read/write requests are accepted, even when there is a read cycle pending. Read/write
requests can pas reads.
Master I/O deferred/split request outstanding maximum count
27
0
• 0 =CCh[26:24]
•1=1
146
April 2004
Developer’s Manual