EW31244SL7QV Datasheet, PDF (89/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.3
5.6.3.1
5.6.3.1.1
Master Aborts on the PCI Interface
As an initiator on the PCI bus, the GD31244 controller may encounter master abort conditions
during:
• Outbound Read Request
• Outbound Write Request
• Outbound Read Completion
As a target, the GD31244 controller PCI interface is capable of signaling a master abort case
during:
• Address Parity Error (Conventional Mode)
• Inbound Read Request (PCI-X Mode)
Master-Aborts Signaled by Intel^® 31244 PCI-X to Serial ATA Controller
as an Initiator
Master Aborts for Outbound Read or Write Request
This error may be encountered in both the Conventional and the PCI-X modes. For an Outbound
transaction, there are two ways in which a Master-Abort may be signaled to the GD31244
controller:
1. In the Conventional or PCI-X modes, a master abort is signaled when the target of the
transaction does not assert DEVSEL# within five clocks (seven clocks when operating in the
PCI-X Mode) of the assertion of FRAME#.
2. In PCI-X mode, the GD31244 controller may initiate a split request (read request) to the
target-side interface of a PCI-to-PCI bridge. When the PCI-to-PCI bridge detects a Master Abort
on its initiating interface for that Split Request, master abort is signaled to GD31244 controller
through a Master-Abort Split Completion Error Message (class=1h - bridge error and index=00h
- Master Abort). The following actions with given constraints are performed by GD31244
controller when a master abort is detected by the PCI initiator interface or the PCI target interface
receives a Master-Abort Split Completion error message:
• Set the Master Abort bit (bit 13) in the SUSR.
• When the transaction is an MSI outbound write and the SERR# Enable bit in the SUCMD is
set, assert SERR#, otherwise no action. When the GD31244 controller asserts SERR#,
additional action is taken:
Set the SERR# Asserted bit in the SUSR
• When operating in PCI-X mode and Master-Abort is signaled through a Split Completion
Error Message, the Received Split Completion Error Message bit in SUPCIXSR is set.
• Set the DMA Error bit and clear the DMA Active bit in the DMA Status register.
Developer’s Manual
April 2004
89