EW31244SL7QV Datasheet, PDF (87/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.2.3
5.6.2.3.1
5.6.2.4
5.6.2.5
Inbound Read Request Data Parity Errors
Immediate Data Transfer
As a target, the GD31244 controller may encounter this error when operating in the Conventional
PCI or PCI-X modes.
Inbound read data parity errors occur when read data delivered from the inbound read queue is
detected as having bad parity by the initiator of the transaction who is receiving the data. The
initiator may optionally report the error to the system by asserting PERR#. As a target device in
this scenario, no action is required and no error bits are set.
Inbound Write Request Data Parity Errors
As a target, the GD31244 controller may encounter this error when operating in the Conventional
or PCI-X modes.
Data parity errors occurring during write operations received by the GD31244 controller may
assert PERR# on the PCI Bus. Specifically, the following actions with the given constraints are
taken by the GD31244 controller:
• PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
following the data phase in which the data parity error is detected on the bus. This is only done
when the Parity Error Response bit in the SUCMD is set.
• The Detected Parity Error bit in the SUSR is set.
Outbound Read Completion Data Parity Errors
As a target, the GD31244 controller may encounter this error when operating in the PCI-X mode.
Data parity errors occurring during read completion transactions that are claimed by the GD31244
controller are recorded, PERR# is asserted (when enabled) and SERR# is asserted (when
enabled). Specifically, the following actions with the given constraints are taken by the GD31244
controller:
• PERR# is asserted three clock cycles following the data phase in which the data parity error is
detected on the bus. This is only done when the Parity Error Response bit in the SUCMD is
set. When the GD31244 controller asserts PERR#, additional actions are taken:
— The Master Parity Error bit in the SUSR is set.
— When the SERR# Enable bit in the SUCMD is set, and the Data Parity Error Recover
Enable bit in the SUPCIXCMD register is clear, assert SERR#, otherwise no action.
When the GD31244 controller asserts SERR#, additional action is taken:
Set the SERR# Asserted bit in the SUSR.
• The Detected Parity Error bit in the SUSR is set.
• Set the DMA Error bit and clear the Active bit in the DMA Status register.
Developer’s Manual
April 2004
87