EW31244SL7QV Datasheet, PDF (18/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
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1.2.5
Table 2.
Terminology
To aid the discussion of the GD31244 controller architecture, the following terminology is used:
Terms and Definitions (Sheet 1 of 2)
Term
Definition
BAR Base Address Register
BIST Built-In Self Test
CFG Configure
CRB Customer Reference Board
signal is comprised of a positive conductor and a negative conductor. The
Differential Signal _{differential signal is the voltage on the positive conductor minus the voltage on the}
negative conductor (i.e., TX+ – TX-).
DMA Direct Memory Access
Downstream At or toward a PCI bus with a higher number (after configuration).
DPA Direct Port Access
Refers to a mode that allows more efficient access to the GD31244 registers. See
also PCI IDE.
DWORD 32-bit data word.
HBA Host Bus Adapter
Host processor: Processor located upstream from the GD31244 controller.
Inbound Transactions
Transactions that are aimed at the GD31244 controller by an external bus master
device.
Inter-symbol interference. Data-dependent deterministic jitter caused by the time
ISI propagated at different rates by the transmission media. This translates into
high-frequency,data-dependent, jitter.
JEDEC Provides standards for the semiconductor industry.
Jitter
Jitter is a high-frequency, semi-random displacement of a signal from its ideal
location.
M/S
Master/Slave. Refers to a legacy ATA mode that uses the traditional methods for
accessing the ATA and the DMA registers (see also DPA).
BAR Base Address Register
MR Memory Read
MRL Memory Read Line
MRM Memory Read Multiple
MSI Message Signalled Interrupts
MW Memory Write
MWI Memory Write and Invalidate
Network
The trace of a PCB that completes an electrical connection between two or more
components.
Outbound Transactions Transactions that are initiated by the controller to another target device.
PATA Parallel ATA
PBGA Plastic Ball Grid Array
PERR# Parity error
PIO Programmed I/O
18
April 2004
Developer’s Manual