EW31244SL7QV Datasheet, PDF (66/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Programming Interface
5
The GD31244 register set is composed of several functional groups, some of which appear at
different addresses and in different spaces (configuration, I/O, memory) when used in PCI IDE
mode or DPA mode. PCI IDE mode is a legacy mode that uses I/O space for backwards
compatibility while DPA mode is a new design using memory space. In PCI IDE mode, PCI ATA
specifications use 5 of the 6 available BAR windows for task file and DMA registers. The Superset
registers use the last BAR (BAR5). All other registers use configuration space.
Besides the required PCI configuration register set, these include:
• the PCI/PCI-X core configuration
• the Serial Expansion ROM registers
• the common port registers
• assorted control registers
In DPA mode, all the (I/O space) registers to which the 6 BAR registers point are consolidated into
a single contiguous (memory space) set of registers to which BAR0/1 points. In addition, several of
the common port registers are moved from the PCI configuration space to the BAR0/1 defined
space. As defined in the PCI Local Bus Specification, BAR0/1 are used to allow for a 64-bit
memory address with BAR0 being the low order 32 bits and BAR1 being the high order 32 bits of
the address. The GD31244 uses mode pin MS_DA to place the device in Master/Slave mode (when
HIGH) or DPA mode (when LOW). This determination is made at power up so I/O and Memory
can be configured correctly.
66
April 2004
Developer’s Manual