EW31244SL7QV Datasheet, PDF (62/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.4
Programmed I/O (PIO)
PIO is an alternate way of transferring data instead of using the DMA Controller. Data is transferred
by the host processor reading or writing the Data Port register of the Command Block. In the ATA
standard, some commands may only use PIO to transfer data. For example, the IDENTIFY DEVICE
command. During PIO reads, data is read from the Data Port register, essentially pulling data from the
head of the receive FIFO, while the serial link is pushing incoming data from the serial link to the tail
of the FIFO.
During PIO writes, data is pushed into the Data Port register. Data written to the Data Port register is
placed at the tail of the speed matching transmit FIFO. The serial link pulls data to transmit from the
head of the FIFO.
IDE devices are sector-based mass storage devices, which means that data is always transferred on
sector boundaries, and therefore a sector is the smallest readable/writable unit. A sector count is
specified as part of the ATA command issued to the device. The minimum sector count may be equal
to one.
The ATA standard supports the following commands for PIO data transfers:
• READ SECTOR
• WRITE SECTOR
• READ MULTIPLE
• WRITE MULTIPLE
The READ SECTOR and READ MULTIPLE are used to read data from the device, whereas the
WRITE SECTOR and WRITE MULTIPLE are used to write data to the device. The READ SECTOR
and WRITE SECTOR commands allow data to be transferred one sector per interrupt. For example,
during a READ SECTOR command, an interrupt is generated by the device to indicate that a sector of
data is ready to be read. After the sector is read, a new interrupt is generated when the next sector is
ready to be transferred and this process continues until the requested sector count is exhausted. The
WRITE SECTOR command also is used to transfer one sector per interrupt. The READ MULTIPLE
and WRITE MULTIPLE commands allow multiple sectors to be transferred per interrupt instead of
one sector per interrupt like the READ SECTOR and WRITE SECTOR commands. Most IDE devices
support this feature and provide a programmable register on the device, which the user may program
using the SET FEATURES command to setup the desired number of sectors to transfer per interrupt.
In both conventional PCI and PCI-X mode, during PIO transfers the GD31244 controller will respond
with a retry when data is not available in the FIFO during reads or when the FIFO is full during writes.
The SATA Unit may be set up during system reset to execute in one of the following modes. Each
mode provides a different programming interface. The DPA_MODE# external strap signal is
sampled during the rising edge of PCI reset, to determine the operation mode.
• PCI IDE Mode
• PCI Direct Port Access Mode
62
April 2004
Developer’s Manual