EW31244SL7QV Datasheet, PDF (154/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.45 SU PCI-X Status Register - SUPCIXSR
Table 83.
This register identifies the capabilities and current operating mode of SATA Unit when operating in
the PCI-X mode.
SU PCI-X Status Register - SUPCIXSR (Sheet 1 of 2)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rc ro ro ro ro ro ro ro ro ro rc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
Bit
31:30
29
28:26
25:23
22:21
20
19
18
17
PCI Configuration Offset
E4H-E7H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
00₂
0₂
001₂
011₂
00₂
0₂
0₂
0₂
1₂
Description
Reserved
Received Split Completion Error Message - This bit is set when the device receives a Split Completion
Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software
writes a 1 to this location.
0 = No Split Completion error message received.
1 = A Split Completion error message has been received.
Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting
of the Maximum Memory Read Byte Count field of the PCIXCMD register:
DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting
1
16
2
32
2
32
2
32
512 (Default)
1024
2048
4096
Designed Maximum Outstanding Split Transactions - The GD31244 controller may have up to four
outstanding split transactions.
Designed Maximum Memory Read Byte Count - The GD31244 controller may generate memory reads
with byte counts up to 512 bytes.
Device Complexity - GD31244 controller is a simple device.
0 = Simple
1 = Complex
Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device
Requester ID is received. Once set, this bit remains set until software writes a 1 to this location.
0 = No unexpected Split Completion has been received.
1 = An unexpected Split Completion has been received.
Split Completion Discarded - This bit is set when the device discards a Split Completion because the
requester does not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus Specification,
Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this location.
0 = No Split Completion has been discarded.
1 = A Split Completion has been discarded.
NOTE: The GD31244 controller will not set this bit since there is no Inbound address responding to
Inbound Read Requests with Split Responses (Memory or Register) that has “read side effects.”
GD31244 controller is a 133 MHz capable device.
154
April 2004
Developer’s Manual