EW31244SL7QV Datasheet, PDF (194/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.8 SU PCI DPA Mode Common SATA Port Registers
This section defines registers that are common to all the four SATA Ports.
5.10.8.1 SU PCI DPA Interrupt Pending Register - SUPDIPR
Table 116.
The SU PCI DPA Interrupt Pending Register is a 32-bit read-only register. This register is used to
report interrupts generated by the SATA ports. Software must clear any pending interrupt at the
appropriate sources. The IDE interrupts (bits 31, 23, 15, 7) are cleared by reading the SATA Port
Command Block Status register. Other pending interrupts in this register are generated by the
SError registers, and must be cleared by writing 1s to the SError registers.
SU PCI DPA Interrupt Pending Register - SUPDIPR (Sheet 1 of 5)
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
DPA Mode BAR0 Offset
000H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
SATA Port 3 IDE Interrupt - When set, this bit indicates that the SATA device generated an interrupt.
31
0₂
This is the same as PCI IDE compatible interrupt. The source of this interrupt is based on the setting of
the ‘I’ bit in the Device-to-Host Register FIS. This interrupt is cleared by reading the taskfile Status
register.
SATA Port 3 CRC Error Detect Interrupt - When set, this bit indicates that a CRC error was detected on
30
0₂
a previous data transfer. The source of this interrupt is from bit 21 (DIAG_C) of the SError register. This
interrupt is cleared by writing a 1 to bit 21 of the SError register. Refer to Section 5.10.12.2, “SU PCI
DPA SATA SError Register - SUPDSSER” on page 222.
SATA Port 3 Data Integrity Interrupt - When set, this bit indicates that a CRC, disparity error was
detected by the host, or an R_ERR primitive was returned by the device in response to a Data FIS
29
0₂
transfer. The source of this interrupt is from bit 8 (ERR_T) of the SError register. This interrupt is cleared
by writing a 1 to bit 8 of the SError register. Refer to Section 5.10.12.2, “SU PCI DPA SATA SError
Register - SUPDSSER” on page 222.
SATA Port 3 Unrecognized FIS Reception Interrupt - When set, this bit indicates that an unsupported
28
0₂
FIS was detected. The source of this interrupt is from bit 10 (ERR_P) of the SError register. This
interrupt is cleared by writing a 1 to bit 10 of the SError register. Refer to Section 5.10.12.2, “SU PCI
DPA SATA SError Register - SUPDSSER” on page 222.
SATA Port 3 R_ERR Primitive Received Interrupt - When set, this bit indicates that an R_ERR primitive
27
0₂
was received during a Data FIS transfer. The source of this interrupt is from bit 22 (DIAG_H) of the
SError register. This interrupt is cleared by writing a 1 to bit 22 of the SError register. Refer to
Section 5.10.12.2, “SU PCI DPA SATA SError Register - SUPDSSER” on page 222.
SATA Port 3 FIFO Error Interrupt - When set, a FIFO error occurred during a Data FIS transfer. The
26
0₂
source of this interrupt is from bit 11 (ERR_E) of the SError register. This interrupt is cleared by writing
a 1 to bit 11 of the SError register. Refer to Section 5.10.12.2, “SU PCI DPA SATA SError Register -
SUPDSSER” on page 222.
194
April 2004
Developer’s Manual