EW31244SL7QV Datasheet, PDF (82/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.5.2 Transmit-Only Mode Testing
The BIST Activate FIS may also be used to place the receiver in a transmit-only mode. The
receiver sends the pattern indicated in the two DWORDs of the BIST Activate FIS that was sent. In
this mode, the GD31244 controller does not check the incoming data patterns. Before sending s
BIST Activate FIS, bit 6 (BIST FIS transmit only bit) must be set and optionally bit 5 (BIST FIS
align bypass bit), bit 4 (BIST FIS scrambling bypass bit), and BIST FIS primitive bit). Bits 5, 4,
and 2 are only used in conjunction with bit 6. Refer to the SATA specification for more details.
Note: To conclude the transmit-only test, the far-end device must be reset using a
COMRESET/COMINIT sequence.
The GD31244 controller may also be setup to send the following patterns to the far-end device:
• A stream of K28.5s. This is done by setting bit 16 of the SU PCI DPA BIST FIS Control and
Status Register - SUPDBFCSR.
• A stream of K28.7s. This is done by setting bit 8 of the SU PCI DPA BIST FIS Control and
Status Register - SUPDBFCSR.
• Content of the SU PCI DPA Host BIST Data Low Register - SUPDHBDLR and the SU PCI
DPA Host BIST Data Low Register - SUPDHBDLR DWORDs. This is done by first loading
SU PCI DPA Host BIST Data Low Register - SUPDHBDLR and SU PCI DPA Host BIST
Data Low Register - SUPDHBDLR with the appropriate values to be transmitted, followed by
setting bit 6 and setting bit 0 of the SU PCI DPA BIST FIS Control and Status Register -
SUPDBFCSR. Bits 5, 4, and 2 of the SU PCI DPA BIST FIS Control and Status Register -
SUPDBFCSR may optionally be set accordingly.
82
April 2004
Developer’s Manual