EW31244SL7QV Datasheet, PDF (171/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.3.6
Table 99.
SU IDE Cylinder Low Register - SUICLR
The SU IDE Cylinder Low Register is a read/write register. The content of the SU IDE Cylinder
Low Register is a command parameter. The content of this register must be loaded before the SU
IDE Command Register is written. The content of the SU IDE Cylinder Low Register is command
dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
SU IDE Cylinder Low Register - SUICLR
PCI
Attributes
7
4
0
rw rw rw rw rw rw rw rw
PCI IDE Mode BAR0/BAR2 Offset
= 04H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07:00
Cylinder Low - This field is dependent on the device access methods. There are three methods:
• CHS Mode: In CHS mode, this field indicates the lower 8 bits of the 16-bit cylinder number identifier.
Device
Dependent ^a
• 28-bit LBA Mode: This field is used for bit positions LBA[15:8] of the 28-bit addressing LBA[27:0].
• 48-bit LBA Mode: This field is used for bit positions LBA[15:8] and LBA[39:32] of the 48-bit
addressing LBA[47:0]. This register acts as a 2-byte FIFO. The higher byte is written first followed
by the lower byte.
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a diagnostic code. The diagnostic
code is device dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
Developer’s Manual
April 2004
171