EW31244SL7QV Datasheet, PDF (150/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.41 SU Arbiter Control - SUACR
Table 79.
This register provides master arbiter control.
SU Arbiter Control Register SUACR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw ro ro ro ro ro ro ro rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
31:30
29:28
27:26
25
24:18
17
16
15:8
7:0
Default
00b
00b
00b
0
0000000b
0
0
0
00h
PCI Configuration Address Offset
D8 - DC
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
Master arbiter control, MSI Request.Used only for Fixed Priority (bit 25 set to 1).
00 = Highest priority
01 = Medium priority
10 = Lowest priority
00 = Reserved
Master arbiter control, Target Split Completion. Used only for Fixed Priority (bit 25 set to 1).
00 = Highest priority
01 = Medium priority
10 = Lowest priority
00 = Reserved
Target Split Completion, New Request, Deferred Read, Deferred Write. Used only for Fixed Priority (bit
25 set to 1).
00 = Highest priority
01 = Medium priority
10 = Lowest priority
00 = Reserved
Fixed/Round Robin priority selector.
1 = Fixed
0 = Round Robin
Reserved
Master retry aborted. Write one to clear.
Master TRDY time out aborted. Write one to clear.
Master retry value:
0 = infinite
1 to FFh.
Master TRDY time out value:
0 = disabled
1 to FFh.
150
April 2004
Developer’s Manual