EW31244SL7QV Datasheet, PDF (54/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.1
4.2.2
Serial Engine
The Serial Engine is transparent to the user. The Serial Engine consists of the three layers:
• Transport Layer
• Link Layer
• PHY Layer
Refer to the Serial ATA Specification for more details.
Register Interface
The GD31244 may be set up to operate in one of the following modes:
• PCI IDE Mode (legacy M/S)
• PCI Direct Port Access Mode
The register interface for each mode is described in Section , “The SATA Unit may be set up during
system reset to execute in one of the following modes. Each mode provides a different
programming interface. The DPA_MODE# external strap signal is sampled during the rising edge
of PCI reset, to determine the operation mode.” on page 62.
54
April 2004
Developer’s Manual