EW31244SL7QV Datasheet, PDF (138/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.30 SU Extended Control and Status Register 0 - SUECSR0
Table 68.
This register is used to control the LED functionality and also to select the superset registers when
in PCI IDE mode.
SU Extended Control and Status Register 0 - SUECSR 0
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rv rw rv rv rv rv rv rv rv rv rv rv rv rw rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw
Bit
31:29
28
27:17
16
15:03
02
01
00
PCI Configuration Address Offset
98H - 9BH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
WO = Write Only
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
000₂
1₂
000H
0₂
0₂
0₂
0₂
0₂
Description
Reserved
LED0 Only:
• When this bit is set all SATA Ports’ activity are reflected on LED0 only. Other LEDs are not used.
• In PCI IDE mode, when this bit is cleared, LED0 reflects the activity for Channel 0 (Port 0 and Port
1) and LED1 reflects the activity for Channel 1 (Port 2 and Port 3).
• In DPA mode, when this bit is cleared, LED0, LED1, LED2, and LED3 reflect the activity for Port 0,
Port 1, Port 2, and Port 3 respectively.
Reserved.
BAR 5 (Superset Features) Secondary Select:
• In PCI IDE mode this bit is a read/write bit and is used to select between the primary and secondary
channel. When set, the secondary channel is selected.
• In DPA mode, this bit is a reserved bit.
Reserved.
Register protect.
• PCI IDE Mode: Register protect. Set this bit to 1 to enable writing the Device ID, Vendor ID, Class
Code, Subclass Code, Interface Code registers and bits 27:24 and 1:0 of this register. Set to 0 to
disable.
• DPA Mode: Register protect. Set this bit to 1 to enable writing the Device ID, Vendor ID, Class Code,
Subclass Code, Interface Code registers and bits 27:24 and 1:0 of this register. Set to 0 to disable.
• PCI IDE Mode: PCI clock domain reset. Write a 1 to this register to reset the host Clk domain. Write
a 0 for normal operation. This bit is write protected by setting bit 2 and write enabled by clearing bit
2.
• DPA Mode: PCI clock domain reset. Write a 1 to this register to reset the hostClk domain. Write a 0
for normal operation. This bit is write protected by setting bit 2 and write enabled by clearing bit 2.
• PCI IDE Mode: SATA clock domain reset. Write a 1 to this register to reset the sclk domain. Write a
0 for normal operation. This bit is write-protected by setting bit 2 and write enabled by clearing bit 2.
• DPA Mode: SATA clock domain reset. Write a 1 to this register to reset the sclk domain. Write a 0 for
normal operation. This bit is write-protected by setting bit 2 and write enabled by clearing bit 2.
138
April 2004
Developer’s Manual