EW31244SL7QV Datasheet, PDF (123/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.15 SU Base Address Register 4 - SUBAR4
Table 53.
The SU Base Address Register 4 (SUBAR4) defines the base I/O address for the DMA functions
for both channel 0 and 1.
SU Base Address Register 4 - SUBAR4
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv ro
PCI Configuration Address Offset
20H - 23H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:04
03:01
00
Default
Description
0000_000H
Base Address 4 - These bits define the base address of the DMA Registers in PCI I/O space for both
channel 0 and 1.
000₂
1₂
Reserved.
I/O Space Indicator - This bit field describes memory or I/O space base address. The SATA Unit in PCI
IDE mode is mapped into I/O space, thus this bit must be one.
Developer’s Manual
April 2004
123