EW31244SL7QV Datasheet, PDF (27/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Overview
2.5
2.5.1
2.5.2
Table 5.
Modes of Operation
The programming interface for the GD31244 has 2 modes of operation: Master/Slave (M/S or PCI
IDE) mode and Direct Port Access (DPA) mode.
Master/Slave Mode (or PCI IDE Mode)
Master/Slave (M/S) mode implements a PCI-native mode standard ATA controller with primary
and secondary channels, each supporting a master and a slave mass storage device (4 SATA
devices in total). M/S mode places the task file in different segments of I/O space and differentiates
within each space between primary and secondary channels. Base Address Register 5 (BAR5)
provides access to the SATA extended register set in I/O space.
Direct Port Access Mode
Direct Port Access (DPA) mode is a new mass storage sub-class that extends the standard task file
interface to include expandable numbers of ports and advanced DMA capabilities. Standard PCI
ATA controllers share the task file interface between the master and slave device, eliminating the
ability to support simultaneous access between a master/slave pair. DPA allows the GD31244 to
support unique task file interfaces between multiple SATA ports. DPA eliminates the parallel ATA
master/slave protocol requirements. DPA access is geared for applications where high data
bandwidth and performance are primary requirements. This mode allows for simultaneous access
to each SATA port for true overlapped I/O capability. Table 5 provides the primary features of the
DPA mode interface.
DPA Mode Interface Features
Features
PCI up to 66 MHz or PCI-X up to
133 MHz
Independent port operation
One DMA Channel per SATA port
Enhanced Interrupt Reporting
Description
Required for bandwidth.
Each SATA port can be controlled independently. Each port’s registers
are available at all time. This includes DMA registers.
By having each SATA port support a DMA channel data to be transferred
between device and memory independently of other devices. The DMA
context can also be maintained.
To report Serial ATA specific events: SError bits, First Party DMA receipt.
While utilizing DPA mode to accomplish an overlapped and independent I/O capability, the block,
control block, DMA and SATA superset registers for each SATA port are available at all times.
DMA context is unique to each port, allowing independent and simultaneous transfers between the
host and each of the SATA ports.
Developer’s Manual
April 2004
27