EW31244SL7QV Datasheet, PDF (95/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.7 PCI Error Summary
Table 17 summarizes the GD31244 controller error reporting for PCI bus errors. The table assumes
that all error reporting is enabled through the appropriate command registers (unless otherwise
noted). The SU Status Register records PCI bus errors. Note that the SERR# Asserted bit in the
Status Register is set only when the SERR# Enable bit in the Command Register is set.
Table 33.
31244 Controller Error Reporting Summary - PCI Interface (Sheet 1 of 3)
Error Condition^a
(Bus Mode^b)
Bits Set in
SU Status Register
(SUSR^c)
or
SU PCI-X Status Register
(SUPCIXSR^d)
PCI IDE Mode
SU IDE Channel 0 DMA
Status Register (SUICDSR0)
or
SU IDE Channel 1 DMA
Status Register (SUICDSR1)
DPA Mode
SU PCI DMA Status Register
(SUPDDSR)
PCI Bus Error Response
(i.e., signal Target-Abort, signal
Master-Abort etc.)
DMA Action
DMA Action
Address or Attribute Parity
Error (Both)
Target Abort (target) - bit 11 of
SUSR for the following
transactions: Configuration Read,
Configuration Write, I/O write, I/O
Read, and Memory Read. Memory
Write and Outbound Read Split
Completion do not signal a target
abort.
None
None
(Both)
SERR# Asserted - bit 14 of SUSR
(Both)
Detected Parity Error - bit 15 of
SUSR
Outbound Read Request _{Signal PERR# (both)}
(Immediate Data Transfer)
Parity Error (Both)
SERR# (PCI-X Mode Only).
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
(Both)
Master Parity Error - bit 8 SUSR
(PCI-X)
SERR# Asserted - bit 14 SUSR
(Both)
Detected Parity Error - bit 15 of
SUSR
Outbound Read Request
(Split Response
Termination) Parity Error
(PCI-X)
Signal PERR# and SERR#
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
(PCI-X)
Master Parity Error - bit 8 SUSR
(PCI-X)
SERR# Asserted - bit 14 SUSR
(PCI-X)
Detected Parity Error - bit 15 of
SUSR
Outbound Read
Completion Parity Error
(PCI-X)
Signal PERR# and SERR#
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
(PCI-X)
Master Parity Error - bit 8 SUSR
(PCI-X)
SERR# Asserted - bit 14 SUSR
(PCI-X)
Detected Parity Error - bit 15 of
SUSR
Outbound Write Request Signal SERR# (only for PCI-X or
Parity Error (Both)
MSI Writes).
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
• Set DMA Error - bit 1
• Clear DMA Active - bit 0
(Both)
Master Parity Error - bit 8 of SUSR
(PCI-X or MSI)
SERR# Asserted - bit 14 of SUSR
Developer’s Manual
April 2004
95