EW31244SL7QV Datasheet, PDF (243/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.19 SU PCI DPA Host DMA Buffer Offset Register - SUPDHDBOR
Table 153.
The SU PCI DPA Host DMA Buffer Offset Register is the fourth DWORD parameter of the SATA
DMA Setup Host-to-Device FIS. Refer to the Serial ATA Specification.
SU PCI DPA Host DMA Buffer Offset Register - SUPDHDBOR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI IDE Mode Offset
= 078H,
DPA Mode Offset
Port 0 = 378H, Port 1 = 578H
Port 2 = 778H, Port 3 = 978H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
31:00
Default
Description
0000_0000H Buffer Offset - This is the byte offset into the DMA buffer region.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Developer’s Manual
April 2004
243