EW31244SL7QV Datasheet, PDF (31/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Overview
2.8.1
2.9
2.10
Reference Clock Generation
A 37.5 MHz reference clock with a +/- 100 ppm accuracy is required for proper operation of the
GD31244. This can be generated from an external oscillator connected directly to the XI input.
Optionally, a 37.5 MHz crystal may be connected between the XI and XO pins with a 20 pF
capacitor from XI to ground and another from XO to ground. The crystal should have the following
characteristics:
• Frequency: 37.5 MHz +/- 100 ppm
• Mode: Fundamental
• Type: “Parallel” resonant
• ESR: 30 Ohms maximum
• Load Capacitance: 20 pF
• Shunt Capacitance: 7 pF
• Drive Level:500 mW maximum
Recommended Vendor/Part Number: Fox Electronics, Part number: 278-37.5-8 (This is an
HC-49SD surface mountable package.) The crystal should be placed near the GD31244 and
isolated from noisy circuits as much as possible.
High-End Storage Features
The GD31244 is well suited for high-end storage applications using Serial ATA drives. The Serial
ATA Direct Port Access mode described above allows the host CPU to initiate overlapping
operations to all four drives. Another feature is a “wide-swing mode” on the four transmitter
outputs which provides approximately double the amplitude of normal operation. This increase
differential voltage swing is useful in connecting to Serial ATA devices over backplanes or
between systems.
JTAG Interface
An IEEE 1149.1 compatible JTAG interface and boundary scan functionality is provided to assist
onboard testing of the device.GD31244
Developer’s Manual
April 2004
31