EW31244SL7QV Datasheet, PDF (165/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.55 SU MSI Message Data Register- SUMSI_Message_Data
The value in the Message Data Register contains the data used during an MSI write transaction.
The GD31244 controller interrupts may be represented by four, two or a single message. Interrupt
handler software will need to read the GD31244 controller interrupt status registers to determine
the cause of the interrupt when more than one source is represented by less than four messages.
Table 93.
During an MSI write data phase, the value in the Message Data Register will be driven on to
AD[15:0] while AD[31:16] will be driven to zero. C/BE[3:0]# are asserted during the data phase
of the memory write transaction.
SU MSI Message Data Register - SUMSI_Message_Data
PCI
Attributes
15
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
15:00
PCI Configuration Offset
FCH - FDH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0000H
Description
Message Data - System software specifies a 16-bit value to be transferred during the data phase of an
MSI write transaction.
Developer’s Manual
April 2004
165