EW31244SL7QV Datasheet, PDF (130/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.22 SU Interrupt Line Register - SUILR
SU Interrupt Line Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2.
This register identifies the system interrupt controller's interrupt request lines which connect to the
device's PCI interrupt request lines (as specified in the interrupt pin register).
In a PC environment, for example, the register values and corresponding connections are:
• 0 (00H) through 15 (0FH) correspond to IRQ0 through IRQ15
• 16 (10H) through 254 (FEH) are reserved
• 255 (FFH) indicates unknown or no connection
Table 60.
The operating system or device driver may examine each device interrupt pin and interrupt line
register to determine which system interrupt request line the device uses to issue requests for
service.
SU Interrupt Line Register - SUILR
PCI
Attributes
7
4
0
rw rw rw rw rw rw rw rw
Bit
07:00
PCI Configuration Address Offset
3CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0EH
Description
Interrupt Assigned - system-assigned value identifies which system interrupt controller interrupt request
line connects to the device's PCI interrupt request lines (as specified in the interrupt pin register).
130
April 2004
Developer’s Manual