EW31244SL7QV Datasheet, PDF (26/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Overview
Figure 2.
As shown in Figure 2, the SATA Unit implements four SATA ports. Each SATA port connects
point-to-point to a SATA device such as a hard drive device using a four-wire serial link. Each
SATA port supports the following features:
• 1 KB transmit/receive FIFO
• DMA Engine with scatter/gather capability
• The SATA Unit supports two operating modes:
— PCI IDE (M/S) Mode
— Direct Port Access Mode
In M/S mode, SATA ports 1 and 2are used to emulate Master/Slave (M/S) operation for the
Primary IDE Channel. Similarly, SATA ports 3 and 4 are used to emulate M/S operation for the
Secondary IDE Channel. These ports are mapped in I/O Space/
In Direct Port Access Mode, each SATA port operates independently and all four SATA ports are
memory-mapped contiguously using one base address register.
Serial ATA Unit Block Diagram
PCI-X
Bus
Serial
ATA
Unit
Port 1
Port 2
Port 3
Port 4
Disk 1
Disk 2
Disk 3
Disk 4
The GD31244 controller allows PCI masters on the PCI bus to initiate transactions to the SATA
Unit ports and allows the SATA port DMAs to initiate transactions to the PCI bus. In M/S mode,
the SATA Unit registers are mapped in the I/O space. Two channels (primary and secondary) are
supported on the GD31244 controller. Each channel consists of four register blocks:
• Command
• Control
• DMA
• SATA Superset
PCI Base Address Register 0 points to the primary channel command block, Base Address Register
1points to the primary channel control block, Base Address Register 2 points to the secondary
channel command block, Base Address Register 3 points to the secondary channel control block,
Base Address Register 4 points to both of the channel DMA register, and Base Address Register 5
defines the base I/O address for the SATA superset registers. Each channel supports its own DMA
controller. The DMA moves data between memory and a device on the channel. There are two
devices per channel for master/slave emulation. Table 3 shows the PCI and PCI-X commands
supported for both inbound and outbound transactions when in M/S Mode.
26
April 2004
Developer’s Manual