EW31244SL7QV Datasheet, PDF (84/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.2
5.6.2.1
5.6.2.1.1
Data Parity Errors on the PCI Interface
Two kinds of data parity errors may occur on the PCI interface:
Errors encountered as an initiator:
• Outbound Read Request
• Outbound Write Request
As an initiator, the GD31244 controller provides an error response for data parity errors on
outbound reads, and data parity errors occurring at the target for outbound writes.
Errors encountered as a target:
• Inbound Read Request (Immediate Data Transfer)
• Inbound Write Request
• Split Completion Messages
• Outbound Read Completion
As a target, the GD31244 controller provides an error response for data parity errors on inbound
writes, inbound configuration writes, and split completion messages. However, there will be no
error response for data parity errors on inbound reads.
Outbound Read Request Data Parity Errors
Immediate Data Transfer
As an initiator, the GD31244 controller may encounter this error condition in Conventional or
PCI-X mode when the target transfers data immediately rather than signalling a Retry¹
(Conventional Delayed Read Request) or a Split Response Termination (PCI-X Split Read
Request).
Data parity errors occurring during read operations initiated by the GD31244 controller are
recorded, PERR# is asserted (when enabled) and SERR# is asserted (when enabled). Specifically,
the following actions with the given constraints are taken by the GD31244 controller:
• PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
following the data phase in which the data parity error is detected on the bus. This is only done
when the Parity Error Response bit in the SUCMD is set. When the GD31244 controller
asserts PERR#, additional actions will be taken:
— The Master Parity Error bit in the SUSR is set.
— When the GD31244 controller is operating in the PCI-X mode, the SERR# Enable bit in
the SUCMD is set, and the Data Parity Error Recover Enable bit in the SUPCIXCMD
register is clear, assert SERR#, otherwise no action. When the GD31244 controller asserts
SERR#, additional action is taken:
Set the SERR# Asserted bit in the SUSR.
• The Detected Parity Error bit in the SUSR is set.
• Set the DMA Error bit and clear the DMA Active bit in the DMA Status register.
1. Retry terminations may also be signaled in PCI-X mode when the target is too busy to handle the current request. However, this is not the
same as a Delayed Read Request in Conventional PCI mode since the requester is not required or expected by the target to return with the
same read request.
84
April 2004
Developer’s Manual