EW31244SL7QV Datasheet, PDF (226/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.4 SU PCI DPA Set Device Bits Register - SUPDSDBR
Table 138.
The SU PCI DPA Set Device Bits Register is a 32-bit register. This register reflects the content of
the Set Device Bit FIS reserved DWORD.
SU PCI DPA Set Device Bits Register - SUPDSDBR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
PCI IDE Mode Offset
= 00CH,
DPA Mode BAR0 Offset
Port 0 = 30CH, Port 1 = 50CH
Port 2 = 70CH, Port 3 = 90CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
Default
Description
This is the SActive Register. The Serial ATA II Native Command Queueing specification defines this
0000_0000H
register as write read. Writing one to any bit will set the bait. The bits are cleared by the device set
device bits FIS word 1 containing a 1 in that bit position. Writing a 0 to these bits by the host will not
clear them.
226
April 2004
Developer’s Manual