EW31244SL7QV Datasheet, PDF (237/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.13 SU PCI DPA Queuing Table Base Address Register
Low - SUPDQTBARL
Table 147.
This register contains the lower values added to the DMA buffer identifier to determine the base
address of the PRD.
SU PCI DPA Device BIST Data High Register - SUPDDBDHR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw ro rw
PCI IDE Mode Offset
= 060H,
DPA Mode Offset
Port 0 = 360H, Port 1 = 560CH
Port 2 = 760H, Port 3 = 960H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
Default
Description
0000_0000H
Value used by the DMA engine to add to the DMA Buffer identifier to get the base address of the PRD,
bits 31:0.
Developer’s Manual
April 2004
237