EW31244SL7QV Datasheet, PDF (124/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.16 SU Base Address Register 5 - SUBAR5
The SU Base Address Register 5 (SUBAR5) defines the base I/O address for the SATA superset
registers. When in PCI IDE mode, the Superset registers for each SATA device on a given channel
are selected by bit 4 (DEV bit) of the Command Block Device/Head register. The Primary and
Secondary channel selection is done by writing bit 16 of the SU Extended Control and Status
Register 0 - SUECSR0. Refer to Section 5.10.2.30, “SU Extended Control and Status Register 0 -
SUECSR0” on page 138.
Table 54.
In PCI IDE mode, the superset registers begins at offset 00H relative to this Base Address Register.
SU Base Address Register 5 - SUBAR5
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv ro
PCI Configuration Address Offset
24H - 27H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:01
00
Default
Description
0000_0000H Base Address 5 - These bits define the base address of the Superset Registers in PCI I/O address space.
1₂
I/O Space Indicator - This bit field describes memory or I/O space base address. The SATA Unit in PCI
IDE mode is mapped into I/O space, thus this bit must be one.
124
April 2004
Developer’s Manual