EW31244SL7QV Datasheet, PDF (59/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.3.3
DMA Error Conditions
When during a DMA transfer, a bus master error condition is encountered like a master abort,
target abort, or a parity error is detected, the SATA port DMA will stop the transfer by clearing the
Active bit in the DMA Status register and setting the Error bit in the DMA Status register. Note that
the SATA port does not generate an interrupt when a bus master operation is aborted. Software will
time out. The following is a list of bus master errors that may be encountered during DMA
transactions. Note that not all bus master error conditions result in the DMA stopping. Refer to
Section 5.6, “PCI Bus Error Conditions” on page 83 for more details.
• Outbound Read Request Data Parity Errors
— Immediate Data Transfer
— Split Response Termination (PCI-X mode)
• Outbound Write Request Data Parity Errors
— Non-MSI Transactions (Message Signaled Interrupts
• Outbound Read Completion Address Parity Error
• Outbound Read Completions Attribute Parity Error
• Outbound Read Completion Data Parity Errors
• Split Completion Error Messages
• Master Abort for Outbound Read Requests
• Master Abort for Outbound Write Requests
• Target Abort for Outbound Read Requests
• Target ABort for Outbound Write Requests
When a requested device transfer (READ DMA or WRITE DMA) does not complete, the software
driver will eventually time out. The software driver is then responsible for clearing the Start bit (bit
0) in the DMA Command register. Note that in this case the Error bit in the DMA Status register
does not get set because there was no bus master error. An example of this type of error condition
may occur when the DMA descriptors specified a smaller transfer size as the programmed transfer
size in the device command. This causes the DMA to complete (DMA active bit cleared) while
leaving the interrupt bit cleared. For example, an interrupt is not generated.
Developer’s Manual
April 2004
59