EW31244SL7QV Datasheet, PDF (163/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.53 SU MSI Message Address Register - SUMSI_Message_Address
Table 91.
The Message address register specifies the DWORD aligned address for the MSI memory write
transaction. The value is set by system software during initialization.
SU MSI Message Address Register - SUMSI_Message_Address
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv
PCI Configuration Offset
F4H- F7H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
31:2 00000000H Message Address - DWORD aligned Message Address. This value is set by system software.
1:0
002
Reserved.
Developer’s Manual
April 2004
163