EW31244SL7QV Datasheet, PDF (57/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.3.1 DMA Operation
To initiate a DMA transfer between memory and a device, the following steps are required:
• Software prepares a descriptor table in memory. Each descriptor is 8 bytes long and consists of
an address pointer to the starting address and the byte count of the data buffer to be transferred.
In a given descriptor table, two consecutive descriptors are offset by 8 bytes and are aligned on
a 4-byte boundary.
• Software provides the starting address of the descriptor table by loading the DMA Descriptor
Table Pointer Register of the DMA controller. The direction of the data transfer is specified by
setting the Read/Write control bit in the DMA Command Register. Clear the interrupt bit and
error bit in the Status Register.
• Software loads the appropriate DMA transfer command in the command block. Examples of
such commands are:
— READ DMA
— WRITE DMA
The command is issued first by loading the command parameters and then writing the
command register.
• Software engages the DMA engine by writing the Start bit in the DMA Command Register.
• The DMA engine transfers data to/from memory responding to the SATA port.
• At the end of the transfer the SATA port signals an interrupt
• In response to the interrupt, software resets the Start/Stop bit in the DMA Command Register.
It then reads the DMA Status register and then the device status register to determine when the
transfer completed successfully.
When a SATA port DMA controller makes a request on the PCI or PCI-X bus and the request is
retried or disconnected, the current SATA port request will be re-attempted until the request is fully
made. The other SATA port DMA will not be able to make requests on the PCI or PCI-X bus until
the current request is either completed or gets a split response.
The DMA controller behaves differently in PCI IDE mode than in DPA mode when fetching the
first DMA descriptor from memory. In PCI IDE mode, for a DMA WRITE command, the first
descriptor fetch is triggered when the first DMA Activate FIS is received from the device. For a
DMA READ command, the first descriptor fetch is triggered when the first Data FIS is received
from the device. In DPA mode, the descriptor fetch is triggered when the Start bit in the DMA
Command register is set regardless of DMA commands.
In both PCI IDE and DPA modes, the initial DMA data transfer is triggered under the same
condition. For a DMA READ command (data is written to system memory), the receipt of the first
Data FIS from the device triggers the data transfer. However, the DMA controller will have to wait
for adequate data to be written into the FIFO, from the device, before it issues a write request to the
bus master. For a DMA WRITE command (data is read from system memory), the receipt of the
first DMA Activate FIS from the device (the same FIS that triggered fetching of the first
descriptor) triggers the data transfer.
Note: During a DMA transfer, when a software reset is issued by writing the SRST bit in the Device
Control register, the DMA controller for that particular port will stop the transfer by clearing the
Active bit in the DMA Status register.
Developer’s Manual
April 2004
57