EW31244SL7QV Datasheet, PDF (159/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.49 SU Power Management Control/Status Register - SUPMCSR
Table 87.
Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
interface for the power management extended capability.
SU Power Management Control/Status Register - SUPMCSR
PCI
Attributes
15
12
8
4
0
ro rv rv rv rv rv rv ro rv rv rv rv rv rv rw rw
PCI Configuration Offset
ECH - EDH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
15
0₂
PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not
supported by the GD31244 controller.
14:9
00H
Reserved
8
0₂
PME_En - This bit is hardwired to read-only 0₂ since this function does not support PME# generation
from any power state.
7:2
000000₂ Reserved
Power State - This 2-bit field is used both to determine the current power state of a function and to set
the function into a new power state. The definition of the values is:
00₂ - D0
1:0
00₂
01₂ - D1 (Unsupported)
10₂ - D2 (Unsupported)
11₂ - D3hot
The GD31244 controller supports only the D0 and D3hot states.
Note:
1. D0 – GD31244 supports D0 state and (as in all PCI compliant devices) will be in the D0 state before use.
After power on reset or transitioning from D3_hot GD31244 is in D0 in an uninitialized state. Once initialized it
is in a D0 active date.
2. D3 – GD31244 supports D3 state. The D3 state has two variants D3_hot and D3_cold. D3_hot the device has VCC
applied to it and D3_cold.the device has VCC removed from it. Removing power will place the device in D3_cold
state. From a D3_cold state the device can transition to a D0 uninitialized state by reapplying Vcc and asserting
a PCI RST#. D3_hot can be transitioned to an uninitialized D0 state through the software writing to the
PMSCR register or having PCI RST# asserted. D3_hot respond to configuration space accesses as long as
their power and clock are supplied. The D3_hot device can go into a D0 uninitialized state by performing a soft
reset (without PCI RST# being asserted).
3. Refer to the PCI Bus Power Management Interface Specification for more information on the power
management states.
Developer’s Manual
April 2004
159