EW31244SL7QV Datasheet, PDF (75/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.3.1
Table 28.
LBA Addressing in PCI IDE Mode
This section describes how the command block registers are utilized in 28-bit and 48-bit LBA
addressing modes. The Device/Head register (bit 6) indicates whether a command is using CHS
(Cylinder/Head/Sector) or LBA address format. When bit 6 of the Device/Head register is set,
LBA address format is being used. Table 28 shows how the command block registers are utilized
for 28-bit LBA addressing.
28-Bit LBA Address Bit Layout in PCI IDE Mode
LBA Bits
Register Bit Location
Register
7
6
5
4
3
2
1
0
Sector Number / LBA Low
7
6
5
4
3
2
1
0
Cylinder Low / LBA Mid
15
14
13
12
11
10
9
8
Cylinder High / LBA High
23
22
21
20
19
18
17
16
Device/Head
N/A
LBA
N/A
DEV
27
26
25
24
Table 29 shows how the command block registers are utilized for 48-bit LBA addressing. To preserve
the same ATA standard programming interface, the Sector Count, LBA Low, LBA Mid, and LBA High
registers are kept as 8-bit registers. Instead, these registers are implemented as 8-bit ports to two-byte
deep FIFOs. Note that the 8-bit port must always be written in pairs, otherwise proper functionality is
not guaranteed. For example, a 16-bit value is loaded to any of these registers by performing two 8-bit
writes. The three 16-bit registers, therefore, provides the 48-bit LBA address bits. The most recently
written value to any of these registers is pushed into the lower byte position and the previous written
value gets pushed into the upper byte position. As an example, when the value 17H is written to
Cylinder Low/LBA Mid register followed by the value 68H to the same register, the value 17H first
goes into LBA[15:8]. After the value 68H is written, the value 17H gets pushed into LBA[39:32] and
the value 68H goes into LBA[15:8]. Table 30 summarizes the loading sequence.
Note: Note that the Device/Head register is not used to form a 48-bit LBA address. However, bits 0-3 of
the Device/Head register must be set high.
Table 29. 48-Bit LBA Address Bit Layout
LBA Bits
Register
Sector Number / LBA Low
Cylinder Low / LBA Mid
Cylinder High / LBA High
Device/Head
7
31/7
39/15
47/23
N/A
6
30/6
38/14
46/22
LBA
Register Bit Location
5
29/5
37/13
45/21
N/A
4
28/4
36/12
44/20
DEV
3
27/3
35/11
43/19
1
2
26/2
34/10
42/18
1
1
25/1
33/9
41/17
1
0
24/0
32/8
40/16
1
Table 30.
48-Bit Address Loading Sequence
Register
Sector Count
Sector Number / LBA Low
Cylinder Low / LBA Mid
Cylinder High / LBA High
Most Recently Written
Sector Count[7:0]
LBA[7:0]
LBA[15:8]
LBA[23:16]
Previous Content
Sector Count[15:8]
LBA[31:24]
LBA[39:32]
LBA[47:40]
Developer’s Manual
April 2004
75