EW31244SL7QV Datasheet, PDF (67/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.1
5.1.1
Table 26.
PCI IDE Mode
The SATA Unit supports both Native-PCI IDE modes. In this mode, the GD31244 conforms to the
PCI IDE Specification - Revision 1.0. In PCI IDE mode, the following registers are available to the
user and are mapped in the I/O space.
• Command Block Registers
• Control Block Registers
• DMA Registers
Native-PCI Mode
In Native-PCI IDE mode, the Command Block Registers and Control Block Registers are
completely relocatable in the I/O space using the PCI Base Address Registers, Section 5.10.2.11,
“SU Base Address Register 0 - SUBAR0” on page 119, Section 5.10.2.12, “SU Base Address
Register 1 - SUBAR1” on page 120, Section 5.10.2.13, “SU Base Address Register 2 - SUBAR2”
on page 121, and Section 5.10.2.14, “SU Base Address Register 3 - SUBAR3” on page 122.
Table 26 shows the Base Address Registers and how they are used.
SATA Port Register Mapping in Native PCI IDE Mode
Configuration Space BAR Offset
Registers
10H
14H
18H
1CH
20H
24H
Primary Channel Command Block
Primary Channel Control Block
Secondary Channel Command Block
Secondary Channel Control Block
Primary and Secondary Channel DMA Registers
SATA Superset Registers
Developer’s Manual
April 2004
67