EW31244SL7QV Datasheet, PDF (121/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.13 SU Base Address Register 2 - SUBAR2
Table 51.
The SU Base Address Register 2 (SUBAR2) defines the base I/O address of the Command Block
Registers for Channel 1.
SU Base Address Register 2 - SUBAR2
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv ro
PCI Configuration Address Offset
18H - 1BH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:04
03
02:01
00
Default
Description
0000_017H
Base Address 2 - These bits define the base address of the Command Block Registers in PCI I/O space
for channel 1.
0₂
Base Address 2 - These bits define the base address of the Command Block Registers in PCI I/O space
for channel 1.
00₂
Reserved.
1₂
I/O Space Indicator - This bit field describes memory or I/O space base address. The SATA Unit in PCI
IDE mode is mapped into I/O space, thus this bit must be one.
Developer’s Manual
April 2004
121