EW31244SL7QV Datasheet, PDF (11/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
50 SU Base Address Register 1 - SUBAR1 .................................................................................. 120
51 SU Base Address Register 2 - SUBAR2 .................................................................................. 121
52 SU Base Address Register 3 - SUBAR3 .................................................................................. 122
53 SU Base Address Register 4 - SUBAR4 .................................................................................. 123
54 SU Base Address Register 5 - SUBAR5 .................................................................................. 124
55 SU Subsystem Vendor ID Register - SUSVIR .......................................................................... 125
56 SU Subsystem ID Register - SUSIR......................................................................................... 126
57 SU Expansion ROM Base Address Register - SUEXROMBAR ............................................... 127
58 SU Capabilities Pointer Register - SU_Cap_Ptr .......................................................................128
59 SU Expansion ROM Base Address - SUEXROM .....................................................................129
60 SU Interrupt Line Register - SUILR ..........................................................................................130
61 SU Interrupt Pin Register - SUIPR............................................................................................ 131
62 SU Minimum Grant Register - SUMGNT .................................................................................. 132
63 SU Maximum Latency Register - SUMLAT .............................................................................. 133
64 SPI Command Register - SPICMDR ........................................................................................134
65 SPI Control Register - SPICNTR .............................................................................................. 135
66 SPI Status Register - SPISTATR.............................................................................................. 136
67 SPI Data Register - SPIDATR .................................................................................................. 137
68 SU Extended Control and Status Register 0 - SUECSR 0 ....................................................... 138
69 SU DMA Control Status Register - SUDCSCR 0...................................................................... 139
70 SU Dummy Register - SUDR.................................................................................................... 140
71 SU Interrupt Status Register - SUISR....................................................................................... 141
72 SU Interrupt Mask Register - SUIMR........................................................................................142
73 SU Transaction Control Register - SUTCR .............................................................................. 143
74 SU Target Split Completion Message Enable Register- SUTSCMER......................................144
75 SU Target Split Completion Message Enable Register- SUTSCMER......................................145
76 SU Transaction Control 2 Register- SUTC2R .......................................................................... 146
77 SU Master Split Completion Message Received with Error Message Register -
SUMSCMREMR ....................................................................................................................... 148
78 SU Master Split Completion Message Received with Error Message Register -
SUMSCMREMR ....................................................................................................................... 149
79 SU Arbiter Control Register SUACR......................................................................................... 150
80 SU PCI-X_Capability Identifier Register - SUPCI-X_Cap_ID ................................................... 151
81 SU PCI-X Next Item Pointer Register - SUPCI-X_Next_Item_Ptr ............................................ 152
82 SU PCI-X Command Register - SUPCIXCMD ......................................................................... 153
83 SU PCI-X Status Register - SUPCIXSR ...................................................................................154
84 SU PM_Capability Identifier Register - SUPM_Cap_ID............................................................ 156
85 SU PM Next Item Pointer Register - SUPM_Next_Item_Ptr..................................................... 157
86 SU Power Management Capabilities Register - SUPMCR ....................................................... 158
87 SU Power Management Control/Status Register - SUPMCSR ................................................ 159
88 SU MSI Capability Identifier Register - SUMSI_Cap_ID........................................................... 160
89 SU MSI Next Item Pointer Register - SUMSI_Next_Ptr............................................................ 161
90 SU MSI Message Control Register - SUMSI_Message_Control .............................................. 162
91 SU MSI Message Address Register - SUMSI_Message_Address ...........................................163
92 SU MSI Message Upper Address Register - SUMSI_Message_Upper_Address .................... 164
93 SU MSI Message Data Register - SUMSI_Message_Data ...................................................... 165
94 SU IDE Data Port Register - SUIDR......................................................................................... 166
95 SU IDE Error Register - SUIER ................................................................................................ 167
96 SU IDE Features Register - SUIFR ..........................................................................................168
97 SU IDE Sector Count Register - SUISCR................................................................................. 169
Developer’s Manual
April 2004
11