EW31244SL7QV Datasheet, PDF (174/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.3.9
Table 102.
SU IDE Status Register - SUISR
The SU PCI DPA Status Register is an 8-bit read-only register. When the SU IDE Status Register is
written, the SU IDE Command Register is written instead. This register provides the status of the
device and the interface. Reading this register implicitly clears any pending interrupt. Instead, the
Alternate Status register may be used to read the status of a device without causing any pending
interrupt to get cleared. Some of the bits in this register are command-dependent and are described
in the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification. Information in this
register is updated by the device sending a Device-to-Host Register FIS or PIO Setup FIS.
SU IDE Status Register - SUISR
PCI
Attributes
7
4
0
ro ro ro ro ro ro ro ro
PCI IDE Mode BAR0/BAR2 Offset
= 07H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
BSY - When this bit is set the interface/device is busy. For example, the device may be working a
07
previous command. This bit is set immediately after the Command register is written and a
Host-to-Device Register FIS is sent to the device, indicating that the interface is busy. The device is then
responsible to clear this bit by sending a PIO Setup FIS or Device-to-Host Register FIS.
06
Device Ready (DRDY Bit) - This bit when set indicates that the device is ready.
05
This bit is command dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6)
Specification.
04
Device ^{This bit is command dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6)}
Dependent^{† Specification.}
03
Data Request (DRQ Bit) - This bit is set when the device is ready to transfer data.
02
This bit is command dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6)
Specification.
01
This bit is command dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6)
Specification.
00
Device Error (ERR Bit) - This bit when set indicates that an error occurred. The SU IDE Error Register -
SUIER provides further error information.
† After power-on, a value of 7FH is returned in this register when read before a device is detected on the serial link. This is consistent with the ATA
standard, indicating that a device is not connected to the cable. After the device is detected and a communication link is established between the
host and the device, a value of 80H will be read. Bit 7 (BSY bit) set indicates that the device has been detected, but is busy executing its
initialization and diagnostics. After the device is done with its initialization and diagnostics sequence, it will send a Device-to-Host Register FIS
with bit 7 (BSY bit) cleared.
174
April 2004
Developer’s Manual