EW31244SL7QV Datasheet, PDF (169/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.3.4
Table 97.
SU IDE Sector Count Register - SUISCR
The SU IDE Sector Count Register is a read/write register. The content of the SU IDE Sector Count
Register is a command parameter. The content of this register must be loaded before the SU IDE
Command Register is written. The content of the SU IDE Sector Count Register is command
dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
SU IDE Sector Count Register - SUISCR
PCI
Attributes
7
4
0
rw rw rw rw rw rw rw rw
PCI IDE Mode BAR0/BAR2 Offset
= 02H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07:00
Sector Count -
Device
Dependent ^a
• This 8-bit field indicates the number of sectors to transfer for a given command.
• In the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification, this register acts as a
2-byte FIFO in order to implement a 16-bit sector number.
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a diagnostic code. The diagnostic
code is device dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
Developer’s Manual
April 2004
169