EW31244SL7QV Datasheet, PDF (222/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.2 SU PCI DPA SATA SError Register - SUPDSSER
This SU PCI DPA SATA SError Register provides the supplemental interface error information to
complement the error information available in the SU PCI DPA Error Register. The SU PCI DPA
SATA SError Register provides all the detected errors accumulated since the last time its was
cleared. This Register is broken into two 16-bit fields. Bits [31:16] contains the DIAG field and bit
[15:0] contains the ERR field.
The ERR field contains error information for use by host software in determining the appropriate
response to the error condition.
The DIAG field contains diagnostic error information for use by diagnostic software in validating
correct operation or isolating failure modes.
Not all the SError bits are implemented on the GD31244 controller.
Table 136.
Refer to the Serial ATA Specification.
SU PCI DPA SATA SError Register - SUPDSSER (Sheet 1 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rv rv rv rv rc rv rv rc rc rc rv rc rv rc rv rv rv rv rc rc rc rc rv rv rv rv rv rv rc rv
PCI IDE Mode BAR5 Offset
= 004H,
DPA Mode BAR0 Offset
Port 0 = 304H, Port 1 = 504H
Port 2 = 704H, Port 3 = 904H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31-26
25
24
23
22
21
20
Default
000000₂
0₂
0₂
0₂
0₂
0₂
0₂
Description
Reserved
DIAG_F - Invalid FIS Type:
When set to one, this bit indicates that the FIS type field was not recognized. For example the FIS is
invalid. This bit is cleared by writing a 1 to it.
DIAG_T - Reserved, not implemented.
DIAG_S - Reserved, not implemented.
DIAG_H - Handshake Error:
When set to one, this bit indicates that one or more R_ERR handshake response was received in
response to frame transmission. Such errors may be the result of a CRC error detected by the receiver.
This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit 3, 11, 19, and 27 of the
SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to Table 116, “SU PCI
DPA Interrupt Pending Register - SUPDIPR” on page 194.
DIAG_C - CRC Error:
When set to one, this bit indicates that one or more CRC errors occurred. This bit is cleared by writing a
1 to it. This bit is reported as an interrupt on bit 6, 14, 22, and 30 of the SATA Interrupt Pending register
for SATA ports 0, 1, 2, and 3 respectively. Refer to Table 116, “SU PCI DPA Interrupt Pending Register -
SUPDIPR” on page 194.
DIAG_D - Disparity Error:
When set to one, this bit indicates that incorrect disparity was detected one or more times since the last
time this bit was cleared. This bit is cleared by writing a 1 to it.
222
April 2004
Developer’s Manual