EW31244SL7QV Datasheet, PDF (28/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Overview
2.5.3
Table 6.
2.5.4
Selecting DPA or M/S Mode
The GD31244 uses mode pin MS_DA to place the device in Master/Slave mode (when HIGH) or
DPA mode (when LOW). This determination is made at power up so I/O and Memory can be
configured correctly. Since a dynamic change in configuration memory and I/O mapping is not
allowed, any mode change requires a power-on reset of the chip. As such, software control of this
mode selection is not provided. The programming interface determines if the GD31244 is in M/S
mode or DPA mode by reading by reading the PCI base class and the subclass values defined
herein. The subclass value for the DPA mode has been assigned by the PCI SIG and is 06h.
PCI/X bus operation is programmed through the configuration register set. This includes the
required PCI register set and user-defined registers that configure split transaction behavior,
message signaled interrupts and other advanced features. Mass storage devices are controlled
through registers accessed via the BAR interface. Registers are divided into functional sets. These
are the task file, bus master and extended register sets. Depending on the mode, these sets may
appear at different addresses, have different bus widths or be extended to provide additional
features. See the required M/S or DPA mode section as appropriate for the application. DPA mode
utilizes a single BAR in memory space to access all register sets and organizes them by channel
with an additional area for common registers.
BAR Register usage in M/S and DPA Modes
BAR
DPA Mode
M/S Mode
0 32-bit device base address
1
32-bit device address extension (for 64-bit
addresses)
2 Reserved
3 Reserved
4 Reserved
5 Reserved
I/O Task File Primary Command
I/O Task File Primary Control
I/OTask File Secondary Command
I/O Task File Secondary Control
I/O Bus Master
I/O Superset Registers
Serial ATA Direct Port Access (DPA) mode is selected when the MS_DA input is LOW. This mode
provides an interface method for SATA host controllers that eliminates the parallel ATA M/S
protocol requirements. DPA access is geared for applications where high data bandwidth and
performance are primary requirements and software compatibility is not mandatory. This mode
allows for simultaneous access to each SATA port for true overlapped I/O capability.
DPA Mode Port Initialization
In DPA mode, the GD31244 powers up with the serial ATA ports disabled. To enable each port,
write 0 then 1 to bits 0:3 of each ports Serial Control Register. For example, to enable port 1: read
BAR0 + 308h; AND the read value with FFFFFFF0h; write the result to BAR0 + 308h; “OR” the
result with 000 0001h; write the result to BAR0 + 308h.
28
April 2004
Developer’s Manual