EW31244SL7QV Datasheet, PDF (39/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.5 Write Enable (WREN) Command
Figure 10.
The EEPROM will power up in the write disable state. Any write command (PROGRAM,
SECT_ERASE and CHIP_ERASE) must therefore be preceded by the WREN command. When
the EEPROM is currently write enabled, the WEN bit in the Status Register will be HIGH. The
write enable (WREN) operation is shown in Figure 10.
Write Enable (WREN) Operation
SCS#
SCLK
SDO
01234567
00000110
SDI
Hi -Z
The WREN command may only be issued when the EEPROM is ready to accept a new command.
When the device is busy, it cannot accept any new commands except RDSR. To issue a WREN
command:
1. Issue a RDSR command to read that the RDY# bit is LOW in the EEPROM’s Status Register
to ensure that the EEPROM is ready to receive a new command.
2. When RDY# is not low, continue issuing RDSR commands until RDY# becomes low.
3. Issue a WREN command by an 8-bit write of 06h to the SPI Command Register at offset 90h.
Developer’s Manual
April 2004
39